On-Chip Supporting Module Access Timing; Figure 2.15 On-Chip Memory Access Cycle; Figure 2.16 Pin States During On-Chip Memory Access (Address Update Mode 1) - Hitachi H8/3062 Hardware Manual

φ
Internal address bus
Internal read signal
Internal data bus
(read access)
Internal write signal
Internal data bus
(write access)
φ
Address bus
AS RD HWR LWR
,
D to D
15

Figure 2.16 Pin States during On-Chip Memory Access (Address Update Mode 1)

2.9.3

On-Chip Supporting Module Access Timing

The on-chip supporting modules are accessed in three states. The data bus is 8 or 16 bits wide,
depending on the internal I/O register being accessed. Figure 2.17 shows the on-chip supporting
module access timing. Figure 2.18 indicates the pin states.
64

Figure 2.15 On-Chip Memory Access Cycle

, ,
High
0
Bus cycle
T state T state
1 2
Address
Read data
Write data
T T
1
Address
High impedance
2