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D.1 Port States in Each Mode
Table D-1 Port States
Pin
Name
Mode
ø
—
P1
to P1
1, 2
7
0
3
P2
to P2
1, 2
7
0
3
P3
to P3
1, 2
7
0
3
P5
to P5
1, 2
3
0
3
:$,7
P6
1, 2
0
P6
0
3
P6
to P6
1, 2
5
3
3
Legend
H:
High
L:
Low
T:
High-impedance state
keep: Input pins are in the high-impedance state; output pins maintain their previous state.
DDR: Data direction register bit
Appendix D Pin States
Hardware
Reset
Standby
State
Mode
Clock output T
T
T
—
—
T
T
T
T
—
—
T
T
T
T
T
T
T
T
—
—
T
T
pin —
—
pin
T
T
T
T
H
T
T
T
Software
Standby
Sleep
Mode
Mode
H
Clock output Clock output
keep
keep
T
keep
keep
keep
keep
keep
T
keep
keep
keep
T
T
keep
keep
keep
keep
T
keep
keep
keep
T
T
keep
keep
keep
keep
T
H
keep
keep
Program
Execution
State
Input port
(DDR = 0)
A
to A
7
0
(DDR = 1)
I/O port
Input port
(DDR = 0)
A
to A
15
8
(DDR = 1)
I/O port
D
to D
7
0
I/O port
Input port
(DDR = 0)
A
to A
19
16
(DDR = 1)
I/O port
:$,7
I/O port
I/O port
:5
5'
$6
,
,
I/O port
527
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