Timer Control Register (Tcr) - Hitachi H8S/2215 Series Hardware Manual

10.3.1

Timer Control Register (TCR)

The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR registers, one for each channel (channels 0 to 2). TCR register settings should be made only
when TCNT operation is stopped.
Bit Bit Name Initial value
7 CCLR2 0
6 CCLR1 0
5 CCLR0 0
4 CKEG1 0
3 CKEG0 0
2 TPSC2 0
1 TPSC1 0
0 TPSC0 0
R/W Description
R/W Counter Clear 2 to 0
R/W These bits select the TCNTcounter clearing source. See
tables 10.3 and 10.4 for details.
R/W
R/W Clock Edge 1 and 0
R/W These bits select the input clock edge. when the input
clock is counted using both edges, the input clock 1 and
2, φ/4 both edges = φ/2 rising edge). If phase counting
mode is used on channels 1, 2, 4, and 5, this setting is
ignored and the phase counting mode setting has priority.
Internal clock edge selection is valid when the input clock
is φ/4 or slower. This setting is ignored if the input clock is
φ/1, or when overflow/underflow of another channel is
selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don't care
R/W Time Prescaler 2 to 0
R/W These bits select the TCNT counter clock. The clock
source can be selected independently for each channel.
R/W
See tables 10.5 to 10.10 for details.
Rev. 3.0, 10/02, page 269 of 686