Refresh Time Constant Register (Rtcor); Access Size And Data Alignment; Connections To Ordinary Devices - Hitachi SH7095 Hardware User Manual

7.2.7

Refresh Time Constant Register (RTCOR)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
RTCOR is an 8-bit read/write register. The values of RTCOR and RTCNT are constantly
compared. When the values correspond, the compare match flag of RTCSR is set and RTCNT is
cleared to 0. When the refresh bit (RFSH) of the individual memory control register is set to 1, a
refresh request signal occurs. The refresh request signal is held until refresh operation is
performed. If the refresh request is not processed before the next match, the previous request
becomes ineffective.
When the CMIE bit of the RTSCR is set to 1, an interrupt request is sent to the controller by this
match signal. The interrupt request is output continuously until the CMF bit of the RTSCR is
cleared. When the CMF bit clears, it only affects the interrupt; it is not cleared by the refresh
request. When a refresh is performed and refresh requests are counted using interrupts, a refresh
can be set simultaneously with the interval timer interrupt.
• Bits 15–8—Reserved bits: These bits always read 0. The write value should always be 0.
7.3

Access Size and Data Alignment

7.3.1

Connections to Ordinary Devices

Byte, word, and longword are supported as access units. Data is aligned based on the data width of
the device. Therefore, reading longword data from a byte-width device requires four read
operations. The bus state controller automatically converts data alignment and data length between
interfaces. The data width for external devices can be connected to either 8 bits, 16 bits or 32 bits
by setting BCR2 (for the CS1–CS3 spaces) or using the mode pins (for the CS0 space). Since the
data width of devices connected to the respective spaces is specified statically, however, the data
width cannot be changed for each access cycle.
136 Hitachi
15 14
— —
0 0
R R
7 6
0 0
R/W R/W R/W
13 12 11
— — —
0 0
R R
5 4
0 0
R/W R/W
10
— —
0 0
R R
3 2
0 0
R/W R/W
9 8
—
0 0
R R
1 0
0 0
R/W