Timer Control Register V0(Tcrv0) - Hitachi H8/3672 Series Hardware Manual

10.3.3

Timer Control Register V0(TCRV0)

TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV,
and controls each interrupt request.
Bit Bit Name Initial Value R/W
7 CMIEB 0
6 CMIEA 0
5 OVIE 0
4 CCLR1 0
3 CCLR0 0
2 CKS2 0
1 CKS1 0
0 CKS0 0
Rev. 1.0, 03/01, page 112 of 280
Description
R/W Compare Match Interrupt Enable B
When this bit is set to 1, interrupt request from the CMFB
bit in TCSRV is enabled.
R/W Compare Match Interrupt Enable A
When this bit is set to 1, interrupt request from the CMFA
bit in TCSRV is enabled.
R/W Timer Overflow Interrupt Enable
When this bit is set to 1, interrupt request from the OVF bit
in TCSRV is enabled.
R/W Counter Clear 1 and 0
R/W These bits specify the clearing conditions of TCNTV.
00: Clearing is disabled
01: Cleared by compare match A
10: Cleared by compare match B
11: Cleared on the rising edge of the TMRIV pin. The
operation of TCNTV after clearing depends on TRGE in
TCRV1.
R/W Clock Select 2 to 0
R/W These bits select clock signals to input to TCNTV and the
counting condition in combination with ICKS0 in TCRV1.
R/W
Refer to table 10-2.