Timer Control Register (Tcr) - Hitachi SH7095 Hardware User Manual

• Bit 1: Timer overflow flag (OVF). Status flag that indicates when the FRC overflows
(H'FFFF goes to H'0000). This flag is cleared by the software and set by the hardware. It
cannot be set by software.
Bit 1 (OVF)
0
1
• Bit 0: Counter clear A (CCLRA). Selects whether or not to clear FRC on compare match A
(signal indicating match of FRC and OCRA).
Bit 0 (CCLRA)
0
1
11.2.6

Timer Control Register (TCR)

Bit:
Bit name:
Initial value:
R/W:
TCR is an 8-bit read/write register that selects the input edge for input capture and selects the
input clock for FRC. TCR is initialized to H'00 by a reset, in the standby mode, and when the
module standby function is used.
• Bit 7: Input edge select (IEDG). IEDG selects whether to capture the input capture input (FTI)
on the falling edge or rising edge.
Bit 7: IEDG
0
1
292 Hitachi
Description
Clear conditions: When OVF = 1, OVF is read and then 0 written to it
(initial value)
Set conditions: When the FRC value goes from H'FFFF to H'0000
Description
Disables FRC clear (initial value)
Clears FRC on compare match A
7 6
IEDGA —
0 0
R/W —
Description
Captures input on falling edge (initial value)
Captures input on rising edge
5 4
— — —
0 0
— — —
3 2
— CKS1
0 0
— R/W
1 0
CKS0
0 0
R/W