Timer Serial Control Register (Tscr) - Hitachi H8/3664 Hardware Manual

Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
Bit 0: ACKB
0
1
15.2.7

Timer Serial Control Register (TSCR)

Bit 7
—
Initial value 1
Read/Write —
TSCR is an 8-bit readable/writable register that controls, the I
TSCR is initialized to H'FC by a reset.
Bits 7 to 2—Reserved: Reserved bits.
2
Bit 1—I C Control Unit Reset (IICRST): Resets the control unit except for the I
When a hang up occurs due to illegal communication during I
can set a port or reset the I
2
Bit 0—I C Transfer Rate Select (IICX): This bit, together with bits CKS2 to CKS0 in ICMR,
selects the transfer rate in master mode. For details, see section 15.2.4, I
(ICMR).
320
Description
Receive mode: 0 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has acknowledged the data
(signal is 0)
Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the
data (signal is 1)
6
—
1
—
2
C control unit without initializing rregisters.
5 4
— —
1 1
— —
3 2
— — IICRST
1 1
— —
2
C interface operating mode.
2
C operation, setting IICRST to 1
2
C Bus Mode Register
(Initial value)
1 0
IICX
0 0
R/W R/W
2
C registers.