Port A Data Direction Register (Paddr); Port A Data Register (Padr) - Hitachi H8S/2215 Series Hardware Manual

9.6.1

Port A Data Direction Register (PADDR)

The individual bits of PADDR specify input or output for the pins of port A.
Bit Bit Name Initial Value
−
7 to Undefined
4
3 PA3DDR 0
2 PA2DDR 0
1 PA1DDR 0
0 PA0DDR 0
9.6.2

Port A Data Register (PADR)

PADR stores output data for the port A pins.
Bit Bit Name Initial Value
−
7 to Undefined
4
3 PA3DR 0
2 PA2DR 0
1 PA1DR 0
0 PA0DR 0
R/W Description
−
Reserved
These bits are undefined and cannot be modified.
W Mode 7:
Setting a PADDR bit to 1 makes the corresponding port A
W
pin an output port, while clearing the bit to 0 makes the
W
pin an input port.
W
Modes 4, 5, and 6:
If address output is enabled by the setting of bits AE3 to
AE0 in PFCR, the corresponding port A pins are address
outputs. When address output is disabled, setting a
PADDR bit to 1 makes the corresponding port A pin an
output port, while clearing the bit to 0 makes the pin an
input port.
R/W Description
−
Reserved
These bits are undefined and cannot be modified.
R/W An output data for a pin is stored when the pin function is
specified to a general purpose output port.
R/W
R/W
R/W
Rev. 3.0, 10/02, page 233 of 686