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11.2
Register Descriptions
11.2.1
Port A Data Direction Register (PADDR)
PADDR is an 8-bit write-only register that selects input or output for each pin in port A.
Bit
PA DDR
7
Initial value
Read/Write
W
Port A is multiplexed with pins TP
be set to 1. For further information about PADDR, see section 8.7, Port A.
11.2.2
Port A Data Register (PADR)
PADR is an 8-bit readable/writable register that stores TPC output data for groups 0 and 1, when
these TPC output groups are used.
Bit
PA
Initial value
Read/Write
R/(W)
Note:
*
Bits selected for TPC output by NDERA settings become read-only bits.
For further information about PADR, see section 8.7, Port A.
7
6
5
PA DDR
PA DDR
6
5
0
0
0
W
W
to TP
7
0
7
6
5
PA
PA
7
6
0
0
0
*
R/(W)
*
R/(W)
4
3
PA DDR
PA DDR
4
3
0
0
W
W
Port A data direction 7 to 0
These bits select input or
output for port A pins
. Bits corresponding to pins used for TPC output must
4
3
PA
PA
5
4
3
0
0
*
R/(W)
*
R/(W)
Port A data 7 to 0
These bits store output data
for TPC output groups 0 and 1
2
1
PA DDR
PA DDR
2
1
0
0
W
W
2
1
PA
PA
2
1
0
0
*
R/(W)
*
R/(W)
*
0
PA DDR
0
0
W
0
PA
0
0
R/(W)
*
387
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