10.9.10 Conflict Between Buffer Register Write And Input Capture; Figure 10.51 Conflict Between Buffer Register Write And Input Capture - Hitachi H8S/2628 Hardware Manual

10.9.10 Conflict between Buffer Register Write and Input Capture

If an input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 10.51 shows the timing in this case.
φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register

Figure 10.51 Conflict between Buffer Register Write and Input Capture

Rev. 1.0, 09/02, page 238 of 568
Buffer register write cycle
T1 T2
Buffer register
address
N
M N
M