Figure 10.51 Contention Between Buffer Register Write And Input Capture; Figure 10.52 Contention Between Overflow And Counter Clearing - Hitachi H8S/2215 Series Hardware Manual

φ
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register

Figure 10.51 Contention between Buffer Register Write and Input Capture

Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and
counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing
takes precedence. Figure 10.52 shows the operation timing when a TGR compare match is
specified as the clearing source, and H'FFFF is set in TGR.

Figure 10.52 Contention between Overflow and Counter Clearing

Contention between TCNT Write and Overflow/Underflow: If there is an up-count or down-
count in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write
takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.53 shows the operation
timing when there is contention between TCNT write and overflow.
Rev. 3.0, 10/02, page 324 of 686
Buffer register write cycle
φ
TCNT input
clock
TCNT H'FFFF
Counter
clear signal
TGF
Disabled
TCFV
T1 T2
Buffer register
address
N
M N
M
H'0000