Figure 8.42 Contention Between General Register Read And Input Capture - Hitachi H8/3062 Hardware Manual

Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T state of a general register read cycle, the value before input capture is read.
3
See figure 8.42.
φ
Address bus
Internal read signal
Input capture signal
GR
Internal data bus

Figure 8.42 Contention between General Register Read and Input Capture

General register read cycle
T T
1 2
GR address
X
X
T
3
M
277