ST STM32L4x6 Reference Manual page 1385

RM0351
Bit 4 TXUNRF: Transmit underrun error flag
Bit 3 RXOVRF: Receive overrun error flag
Bit 2 RXBERF: Receive CRC error flag
Bit 1 TXBEF: Transmit buffer empty flag
Bit 0 RXBFF: Receive buffer full flag
This flag is set by hardware to indicate an underrun during the payload transmission i.e.
SWPMI_TDR has not been written in time by the software or the DMA. It is cleared by
software, writing 1 to the CTXUNRF bit in the SWPMI_ICR register.
0: No underrun error in transmission
1: Underrun error in transmission detected
This flag is set by hardware to indicate an overrun during the payload reception, i.e.
SWPMI_RDR has not be read in time by the software or the DMA. It is cleared by software,
writing 1 to CRXOVRF bit in the SWPMI_ICR register.
0: No overrun in reception
1: Overrun in reception detected
This flag is set by hardware to indicate a CRC error in the received frame. It is set
synchronously with RXBFF flag. It is cleared by software, writing 1 to CRXBERF bit in the
SWPMI_ICR register.
0: No CRC error in reception
1: CRC error in reception detected
This flag is set by hardware to indicate that no more SWPMI_TDR update is required to
complete the current frame transmission. It is cleared by software, writing 1 to CTXBEF bit in
the SWPMI_ICR register.
0: Frame transmission buffer no yet emptied
1: Frame transmission buffer has been emptied
This flag is set by hardware when the final word for the frame under reception is available in
SWPMI_RDR. It is cleared by software, writing 1 to CRXBFF bit in the SWPMI_ICR register.
0: The last word of the frame under reception has not yet arrived in SWPMI_RDR
1: The last word of the frame under reception has arrived in SWPMI_RDR
Single Wire Protocol Master Interface (SWPMI)
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