Serial Status Register (Ssr) - Hitachi H8S/2215 Series Hardware Manual

13.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot be
written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared.
Bit Bit Name Initial Value
7 TDRE 1
6 RDRF 0
Note: * The write value should always be 0 to clear the flag.
R/W Description
R/(W)* Transmit Data Register Empty
Displays whether TDR contains transmit data.
[Setting conditions]
· When the TE bit in SCR is 0
· When data is transferred from TDR to TSR and data
can be written to TDR
[Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt request
and writes data to TDR
R/(W)* Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
· When serial reception ends normally and receive data
is transferred from RSR to RDR
[Clearing conditions]
· When 0 is written to RDRF after reading RDRF = 1
· When the DTC is activated by an RXI interrupt and
transferred data from RDR
RDR and the RDRF flag are not affected and retain their
previous values when the RE bit in SCR is cleared to 0.
The RDRF flag is not affected and retains their previous
values when the RE bit in SCR is cleared to 0.
Rev. 3.0, 10/02, page 367 of 686