Serial Status Register (Ssr)-H'ffdc - Hitachi H8/329 Series Hardware Manual

8.2.7 Serial Status Register (SSR)—H'FFDC
Bit 7
TDRE
Initial value 1
Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
Note: * Software can write a "0" to clear the flags, but cannot write a "1" in these bits.
The SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 at a
reset and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when the TDR contents have
been transferred to the TSR and the next character can safely be written in the TDR.
Bit 7
TDRE Description
0 To clear TDRE, the CPU must read TDRE after it has been set to "1,"
then write a "0" in this bit.
1 This bit is set to 1 at the following times:
(1) When TDR contents are transferred to the TSR.
(2) When the TE bit in the SCR is cleared to "0."
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to the RDR.
Bit 6
RDRF Description
0 To clear RDRF, the CPU must read RDRF after
it has been set to "1," then write a "0" in this bit.
1 This bit is set to 1 when one character is received without error and
transferred from the RSR to the RDR.
6 5
RDRF ORER FER
0 0
174
4 3 2
PER TEND
0 0 1
R
1 0
MPB MPBT
0 0
R R/W
(Initial value)
(Initial value)