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Level 7 interrupt?
Mask level 6
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2
5.6.3
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
Program execution status
Interrupt generated?
Yes
No
Yes
Level 6 interrupt?
No
or below?
Yes
Save PC, CCR, and EXR
Update mask level
Read vector address
Branch to interrupt handling routine
No
Yes
NMI
No
No
Yes
No
Mask level 5
or below?
Yes
Clear T bit to 0
No
Level 1 interrupt?
Yes
No
Mask level 0?
Yes
Hold
pending
Rev. 1.0, 09/02, page 79 of 568
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