Timing Of Interrupt Exception-Handling Sequence; Interrupts During Operation Of The Data Transfer Controller - Hitachi H8/500 Series Hardware Manual

Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
2m
Notes:
1. PC: The address of the next instruction to be executed is saved.
2. Register saving and restoring must start at an even address (e.g 2m).
Figure 5-3 (b) Stack before and after Interrupt Exception-Handling

5.4.3 Timing of Interrupt Exception-Handling Sequence

Figure 5-4 shows the timing of the exception-handling sequence for an interrupt when the
program area and stack area are both in on-chip memory and the user-coded interrupt handling
routine starts at an even address.

5.5 Interrupts During Operation of the Data Transfer Controller

If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the
data transfer cycle has been completed and the next instruction has been executed. This is true
even if the interrupt is an NMI. An example is shown below.
(Example)
ADD.W
MOV.W
ADD.W
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Stack area
(Before)
(Maximum Mode)
Program flow
R2, R0
R0, @H'FF00
@H' FF02,R0
Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
SP
2m
Save to stack
DTC interrupt request
Data transfer cycle request
After data transfer cycle, CPU executes next
instruction before starting exception handling
To NMI exception handling sequence
108
Upper 8 bits of SR
Lower 8 bits of SR
Don't care
CP
Upper 8 bits of PC
Lower 8 bits of PC
(After)
NMI interrupt
SP