Setting Of Compare Match Flags Cmfa And Cmfb; Timer Output Timing; Timing Of Compare Match Clear; Figure 11.5 Timing Of Cmf Setting - Hitachi H8S/2215 Series Hardware Manual

11.5.2

Setting of Compare Match Flags CMFA and CMFB

The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input. Figure
11.5 shows this timing.
ø
TCNT
TCOR
Compare match
signal
CMF
11.5.3

Timer Output Timing

When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR. Figure 11.6 shows the timing when the output is set to toggle at compare match A.
ø
Compare match A
signal
Timer output pin
11.5.4

Timing of Compare Match Clear

The timer counter is cleared when compare match A or B occurs, depending on the setting of the
CCLR1 and CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation.
Rev. 3.0, 10/02, page 336 of 686
N
N

Figure 11.5 Timing of CMF Setting

Figure 11.6 Timing of Timer Output

N+1