Figure 10.45 Contention Between Tcnt Write And Clear Operations; Figure 10.46 Contention Between Tcnt Write And Increment Operations - Hitachi H8S/2215 Series Hardware Manual

φ
Address
Write signal
Counter clear
signal
TCNT

Figure 10.45 Contention between TCNT Write and Clear Operations

Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2
state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented.
Figure 10.46 shows the timing in this case.
φ
Address
Write signal
TCNT input
clock
TCNT

Figure 10.46 Contention between TCNT Write and Increment Operations

Contention between TGR Write and Compare Match: If a compare match occurs in the T2
state of a TGR write cycle, the TGR write takes precedence and the compare match signal is
inhibited. A compare match does not occur even if the same value as before is written. Figure
10.47 shows the timing in this case.
TCNT write cycle
T1 T2
TCNT address
N H'0000
TCNT write cycle
T1 T2
TCNT address
N M
TCNT write data
Rev. 3.0, 10/02, page 321 of 686