Contention Between 8Tcnt Write And Increment - Hitachi H8/3008 Hardware Manual

9.7.2

Contention between 8TCNT Write and Increment

If an increment pulse occurs in the T state of a 8TCNT write cycle, writing takes priority and
3
8TCNT is not incremented. Figure 9.19 shows the timing in this case.
8TCNT write cycle
T T T
1 2 3
φ
Address bus 8 TCNT address
Internal write signal
8TCNT input clock
8TCNT N M
8TCNT write data
Figure 9.19 Contention between 8TCNT Write and Increment
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