Itu Output Timing - Hitachi H8/3048 Hardware Manual

10.4.9 ITU Output Timing

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The ITU outputs from channels 3 and 4 can be disabled by bit settings in TOER or by an external
trigger, or inverted by bit settings in TOCR.
Timing of Enabling and Disabling of ITU Output by TOER: In this example an ITU output is
disabled by clearing a master enable bit to 0 in TOER. An arbitrary value can be output by
appropriate settings of the data register (DR) and data direction register (DDR) of the
corresponding input/output port. Figure 10-54 illustrates the timing of the enabling and disabling
of ITU output by TOER.
T T T
1 2 3
ø
Address bus TOER address
TOER
Timer output I/O port
ITU output pin
ITU output Generic input/output
Figure 10-54 Timing of Disabling of ITU Output by Writing to TOER (Example)
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