Figure 10.32 Output Compare Output Timing; Figure 10.33 Input Capture Input Signal Timing - Hitachi H8S/2628 Hardware Manual

φ
TCNT
input clock
TCNT
TGR
Compare
match signal
TIOC pin
Input Capture Signal Timing: Figure 10.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.34 shows the
timing when counter clearing on compare match is specified, and figure 10.35 shows the timing
when counter clearing on input capture is specified.
N
N

Figure 10.32 Output Compare Output Timing

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Figure 10.33 Input Capture Input Signal Timing

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N+1 N+2
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Rev. 1.0, 09/02, page 225 of 568
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