Wait Control Register (Wcr) - Hitachi SH7095 Hardware User Manual

7.2.3

Wait Control Register (WCR)

Bit:
Bit name:
Initial value:
R/W:
Bit:
Bit name:
Initial value:
R/W:
Do not access a space other than CS0 until the settings for register initialization are completed.
• Bits 15–8—Idles between Cycles for Areas 3 to 0 (IW31–IW00): These bits specify idle
cycles inserted between consecutive access to different areas. Idles are used to prevent data
conflict between ROM or the like, which is slow to turn the read buffer off, and fast memories
and I/O interfaces. Even when access is to the same area, idle cycles must be inserted when a
read access is followed immediately by a write access. The idle cycles to be inserted comply
with the area specification of the previous access.
IW31, IW21, IW11, IW01 IW30, IW20, IW10, IW00 Description
0
1
• Bits 7–0—Wait Control of Areas 3 to 0 (W31–W00)
During the basic cycle:
W31, W21, W11, W01
0
0
1
1
128 Hitachi
15 14
IW31 IW30 IW21
1 0
R/W R/W
7 6
W31 W30
1 1
R/W R/W
0
1
0
1
W30, W20, W10, W00
0
1
0
1
13 12
IW20 IW11
1 0
R/W R/W
5 4
W21 W20 W11
1 1
R/W R/W
No idle cycle
Inserts one idle cycle
Inserts two idle cycles (Initial value)
Reserved (do not set)
Description
External wait input disabled without wait
External wait input enabled with one wait
External wait input enabled with two waits
Complies with the long wait specification of
bus control register 1 (BCR1). External wait
input is enabled (Initial value).
11 10
IW10 IW01
1 0
R/W R/W
3 2
W10 W01
1 1
R/W R/W
9 8
IW00
1 0
R/W R/W
1 0
W00
1 1
R/W R/W