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ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as 2-state access space or 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn
Description
0
Area n is designated as 2-state access space
Wait state insertion in area n external space access is disabled
1
Area n is designated as 3-state access space
Wait state insertion in area n external space access is enabled
4.2.3
Wait Control Registers A and B (WTCRA, WTCRB)
WTCRA and WTCRB are 16-bit readable/writable registers that select the number of program
wait states for each area.
Program waits are not inserted in on-chip memory or internal I/O register access.
WTCRA and WTCRB are initialized to H'7777 by a reset and in hardware standby mode. They
are not initialized in software standby mode.
WTCRA
Bit
15
—
Initial value
0
Read/Write
R
Bit
7
—
Initial value
0
Read/Write
R
98
14
13
W72
W71
1
1
R/W
R/W
6
5
W52
W51
1
1
R/W
R/W
12
11
W70
—
1
0
R/W
R
4
3
W50
—
1
0
R/W
R
(Initial value)
(n = 7 to 0)
10
9
W62
W61
1
1
R/W
R/W
2
1
W42
W41
1
1
R/W
R/W
8
W60
1
R/W
0
W40
1
R/W
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