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Manuals and User Guides for NXP Semiconductors freescale MKV41F64VLF15. We have
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NXP Semiconductors freescale MKV41F64VLF15 manual available for free PDF download: Reference Manual
NXP Semiconductors freescale MKV41F64VLF15 Reference Manual (1360 pages)
Brand:
NXP Semiconductors
| Category:
Microcontrollers
| Size: 16.23 MB
Table of Contents
Chapter 1 About this Document
61
Numbering Systems
61
Typographic Notation
62
Special Terms
62
Chapter 2 Introduction
63
Module Functional Categories
63
ARM® Cortex®-M4 Core Modules
64
System Modules
65
Security and Integrity Modules
66
Analog Modules
67
Timer Modules
67
Communication Interfaces
69
Human-Machine Interfaces
69
Chapter 3 Core Overview
73
ARM Cortex-M4 Core Configuration
73
Buses, Interconnects, and Interfaces
74
System Tick Timer
74
Debug Facilities
74
Core Privilege Levels
75
Nested Vectored Interrupt Controller (NVIC) Configuration
75
Interrupt Priority Levels
75
Non-Maskable Interrupt
75
Interrupt Vector Assignments
76
Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration
79
Wake-Up Sources
80
FPU Configuration
80
JTAG Controller Configuration
81
Chapter 4 Memories and Memory Interfaces
83
Flash Memory Types
83
Flash Memory Sizes
83
Flash Security
84
Flash Modes
84
Erase All Flash Contents
84
FTFA_FOPT Register
85
SRAM Sizes
85
SRAM Retention in Low Power Modes
87
System Register File
87
Chapter 5 Memory Map
89
System Memory Map
89
Peripheral Memory Map
90
Read-After-Write Sequence and Required Serialization of Memory Operations
91
Peripheral Bridge 0 (AIPS-Lite 0) Memory Map
91
Chapter 6 Clock Distribution
95
High-Level Device Clocking Diagram
95
Clock Definitions
96
Internal Clocking Requirements
97
Clock Divider Values after Reset
98
VLPR Mode Clocking
99
Clock Gating
99
Module Clocks
100
WDOG Clocking
101
Debug Trace Clock
102
PMC 1-Khz LPO Clock
102
PORT Digital Filter Clocking
102
LPTMR Clocking
103
Flexcan Clocking
103
UART Clocking
104
Chapter 7 Power Management
105
Clocking Modes
105
Partial Stop
105
DMA Wakeup
106
Compute Operation
107
Peripheral Doze
108
Power Modes
109
Module Operation in Low Power Modes
110
Power Modes Shutdown Sequencing
113
Flash Program Restrictions
114
Chapter 8 Security
115
Security Interactions with Other Modules
116
Security Interactions with Debug
116
Chapter 9 Debug
117
The Debug Port
119
JTAG-To-SWD Change Sequence
119
Debug Port Pin Descriptions
120
JTAG Status and Control Registers
120
MDM-AP Control Register
122
MDM-AP Status Register
123
Debug Resets
124
Debug in Low Power Modes
126
Debug Module State in Low Power Modes
127
Debug & Security
127
Chapter 10 Reset and Boot
129
Power-On Reset (POR)
130
System Resets
130
External Pin Reset (PIN)
131
Reset Pin Filter
131
Software Reset (SW)
133
Lockup Reset (LOCKUP)
133
MDM-AP System Reset Request
133
JTAG Reset
134
Ntrst Reset
134
Resetting the Debug Subsystem
134
Boot Sources
135
FOPT Boot Options
135
Boot Sequence
136
Chapter 11 Signal Multiplexing
139
Port Control and Interrupt Module Features
139
Signal Multiplexing Constraints
141
Pinout Diagrams
146
Chapter 12 Port Control and Interrupts (PORT)
151
Modes of Operation
152
Run Mode
152
Stop Mode
152
Debug Mode
153
External Signal Description
153
Detailed Signal Description
153
Memory Map and Register Definition
153
Pin Control
166
Global Pin Control
167
External Interrupts
167
Digital Filter
168
Chapter 13 System Integration Module (SIM)
171
Memory Map and Register Definition
172
Functional Description
211
Chapter 14 Kinetis Flashloader
213
Memory Maps
214
Startup Process
215
Clock Configuration
217
Flashloader Protocol
217
Command with no Data Phase
217
Command with Incoming Data Phase
218
Process Data
219
Command with Outgoing Data Phase
220
Flashloader Packet Types
222
Ping Packet
222
Ping Response Packet
223
Framing Packet
224
Command Packet
225
Data Packet
227
Response Packet
227
Flashloader Command API
229
Getproperty Command
229
Setproperty Command
231
Flasheraseall Command
233
Flasheraseregion Command
234
Fillmemory Command
235
Writememory Command
237
Process Data
238
Read Memory Command
239
Execute Command
241
Reset Command
241
Peripherals Supported
242
SPI Peripheral
244
UART Peripheral
246
Get/Setproperty Command Properties
251
Property Definitions
252
Kinetis Flashloader Status Error Codes
253
Chapter 15 Reset Control Module (RCM)
255
Reset Memory Map and Register Descriptions
255
Chapter 16 System Mode Controller (SMC)
265
Modes of Operation
265
Memory Map and Register Descriptions
267
Functional Description
273
Power Mode Transitions
273
Power Mode Entry/Exit Sequencing
276
Stop Mode Entry Sequence
276
Stop Mode Exit Sequence
276
Run Modes
277
Very-Low Power Run (VLPR) Mode
278
High Speed Run (HSRUN) Mode
279
WAIT Mode
279
Very-Low-Power Wait (VLPW) Mode
280
Stop Modes
280
Stop Mode
281
Very-Low-Power Stop (VLPS) Mode
281
Very-Low-Leakage Stop (Vllsx) Modes
281
Chapter 17 Miscellaneous Control Module (MCM)
285
Memory Map/Register Descriptions
285
Functional Description
292
Chapter 18 Power Management Controller (PMC)
295
Low-Voltage Detect (LVD) System
295
LVD Reset Operation
296
LVD Interrupt Operation
296
Low-Voltage Warning (LVW) Interrupt Operation
296
Memory Map and Register Descriptions
297
Chapter 19 Low-Leakage Wakeup Unit (LLWU)
303
Modes of Operation
304
Block Diagram
305
LLWU Signal Descriptions
305
Memory Map/Register Definition
306
Functional Description
328
Chapter 20 Crossbar Switch Lite (AXBS-Lite)
331
Crossbar-Light Switch Configuration
331
Crossbar Switch Slave Assignments
332
Memory Map / Register Definition
333
General Operation
333
Arbitration During Undefined Length Bursts
334
Fixed-Priority Operation
335
Round-Robin Priority Operation
335
Initialization/Application Information
336
Chapter 21 Peripheral Bridge (AIPS-Lite)
337
Functional Description
351
Access Support
352
Chapter 22 Direct Memory Access Multiplexer (DMAMUX)
353
DMA Transfers Via PIT Trigger
355
Modes of Operation
356
External Signal Description
357
Memory Map/Register Definition
357
DMAMUX Memory Map
357
DMA Channels with Periodic Triggering Capability
359
DMA Channels with no Triggering Capability
361
Always-Enabled DMA Sources
362
Initialization/Application Information
363
Enabling and Configuring Sources
363
Chapter 23 Direct Memory Access Controller (Edma)
367
Edma System Block Diagram
367
Block Parts
368
Modes of Operation
370
Memory Map/Register Definition
371
TCD Memory
371
TCD Initialization
371
TCD Structure
372
Reserved Memory and Bit Fields
372
DMA Memory Map
372
Functional Description
425
Edma Basic Data Flow
425
Fault Reporting and Handling
428
Channel Preemption
431
Initialization/Application Information
435
Edma Initialization
435
Programming Errors
437
Arbitration Mode Considerations
438
Fixed Channel Arbitration
438
Round-Robin Channel Arbitration
438
Performing DMA Transfers
438
Single Request
438
Multiple Requests
440
Using the Modulo Feature
442
Monitoring Transfer Descriptor Status
442
Testing for Minor Loop Completion
442
Reading the Transfer Descriptors of Active Channels
443
Checking Channel Preemption Status
444
Channel Linking
444
Dynamic Programming
445
Dynamically Changing the Channel Priority
445
Dynamic Channel Linking
446
Dynamic Scatter/Gather
447
Chapter 24 External Watchdog Monitor (EWM)
451
Modes of Operation
453
Stop Mode
453
Debug Mode
453
Block Diagram
453
EWM Signal Descriptions
454
Memory Map/Register Definition
454
Functional Description
457
EWM Counter
459
EWM Compare Registers
459
EWM Refresh Mechanism
459
EWM Interrupt
460
Chapter 25 Watchdog Timer (WDOG)
461
WDOG Clocks
461
WDOG Low-Power Modes
461
Functional Overview
463
Unlocking and Updating the Watchdog
465
Watchdog Configuration Time (WCT)
466
Refreshing the Watchdog
467
Windowed Mode of Operation
467
Watchdog Disabled Mode of Operation
467
Debug Modes of Operation
468
Testing the Watchdog
468
Quick Test
469
Backup Reset Generator
471
Generated Resets and Interrupts
471
Memory Map and Register Definition
472
Refresh and Unlock Operations with 8-Bit Access
479
Restrictions on Watchdog Operation
480
Chapter 26 Inter-Peripheral Crossbar Switch a (XBARA)
483
Modes of Operation
487
Block Diagram
487
Signal Descriptions
488
Memory Map and Register Descriptions
489
Interrupts and DMA Requests
511
Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB)
513
Memory Map and Register Descriptions
515
Modes of Operation
524
External Signal Description
524
Functional Description
529
Chapter 29 Oscillator (OSC)
533
Features and Modes
533
Block Diagram
534
OSC Signal Descriptions
534
External Crystal / Resonator Connections
535
External Clock Connections
536
OSC Memory Map/Register Definition
537
OSC Module States
539
Oscillator Startup
541
Oscillator Stable
541
External Clock Mode
541
OSC Module Modes
541
Low-Frequency, High-Gain Mode
542
Low-Frequency, Low-Power Mode
542
High-Frequency, High-Gain Mode
543
High-Frequency, Low-Power Mode
543
Reference Clock Pin Requirements
543
Low Power Modes Operation
544
Chapter 30 Multipurpose Clock Generator (MCG)
545
Modes of Operation
549
External Signal Description
549
Memory Map/Register Definition
549
Functional Description
561
MCG Mode State Diagram
561
MCG Modes of Operation
562
MCG Mode Switching
565
Low-Power Bit Usage
566
MCG Internal Reference Clocks
566
MCG Internal Reference Clock
566
External Reference Clock
567
MCG Fixed Frequency Clock
567
MCG PLL Clock
567
MCG Auto TRIM (ATM)
568
Initialization / Application Information
569
MCG Module Initialization Sequence
569
Initializing the MCG
569
Using a 32.768 Khz Reference
571
Example 2: Moving from PEE to BLPI Mode: MCGOUTCLK Frequency =32 Khz
577
Chapter 31 Flash Memory Controller (FMC)
581
Modes of Operation
582
External Signal Description
582
Functional Description
603
Default Configuration
603
Configuration Options
603
Speculative Reads
604
Initialization and Application Information
605
Chapter 32 Flash Memory Module (FTFA)
607
Program Flash Memory Features
608
Other Flash Memory Module Features
608
Block Diagram
608
Memory Map and Registers
610
Flash Configuration Field Description
611
Program Flash IFR Map
611
Program Once Field
612
Register Descriptions
612
Functional Description
626
Flash Protection
626
Flash Access Protection
627
Flash Operation in Low-Power Modes
629
Stop Mode
629
Flash Reads and Ignored Writes
629
Read While Write (RWW)
629
Flash Program and Erase
630
Flash Command Operations
630
Command Write Sequence
630
Load the FCCOB Registers
631
Launch the Command by Clearing CCIF
631
Command Execution and Error Reporting
631
Flash Commands
632
Margin Read Commands
633
Flash Command Description
634
Read 1S Section Command
635
Program Check Command
636
Read Resource Command
637
Program Longword Command
638
Erase Flash Sector Command
640
Suspending an Erase Flash Sector Operation
640
Resuming a Suspended Erase Flash Sector Operation
641
Aborting a Suspended Erase Flash Sector Operation
641
Read 1S All Blocks Command
643
Read Once Command
644
Program Once Command
645
Erase All Blocks Command
646
Triggering an Erase All External to the Flash Memory Module
647
Verify Backdoor Access Key Command
647
Changing the Security State
649
Unsecuring the Chip Using Backdoor Key Access
649
Reset Sequence
650
Chapter 33 Cyclic Redundancy Check (CRC)
651
Block Diagram
651
Modes of Operation
652
Low-Power Modes (Wait or Stop)
652
Functional Description
655
CRC Initialization/Reinitialization
656
CRC Calculations
656
Transpose Feature
657
Types of Transpose
657
CRC Result Complement
659
Zero Crossing
663
Block Diagram
664
External Signal Descriptions
665
Memory Map and Registers
666
Functional Description
704
Normal Mode Operation
710
ADC Data Processing
712
Scan Sequencing
714
Low Power Modes
715
Timing Specifications
721
Chapter 35 Comparator (CMP)
723
Chip-Specific CMP Information
723
CMP External References
725
External Window/Sample Input
725
CMP Features
726
6-Bit DAC Key Features
726
ANMUX Key Features
727
CMP, DAC and ANMUX Diagram
727
CMP Block Diagram
728
Functional Description
736
CMP Functional Modes
736
Wait Mode Operation
746
Stop Mode Operation
747
Background Debug Mode Operation
747
Start-Up and Operation
747
Low Pass Filter
748
Enabling Filter Modes
748
Latency Issues
749
CMP Interrupts
750
CMP Asynchronous DMA Support
750
Digital-To-Analog Converter
751
DAC Functional Description
751
Voltage Reference Source Select
752
DAC Resets
752
DAC Clocks
752
DAC Interrupts
752
CMP Trigger Mode
752
12-Bit DAC Instantiation Information
753
12-Bit DAC Output
753
12-Bit DAC Reference
753
Block Diagram
754
Memory Map/Register Definition
755
DAC Data Buffer Operation
761
DAC Data Buffer Interrupts
762
Modes of DAC Data Buffer Operation
762
DMA Operation
763
Low-Power Mode Operation
763
Chapter 37 Pulse Width Modulator a (Pwma/Eflexpwm)
765
Modes of Operation
767
Block Diagram
768
Control Signals
771
Memory Map and Registers
772
Functional Description
826
Edge Aligned Pwms
828
Double Switching Pwms
831
ADC Triggering
831
Synchronous Switching of Multiple Outputs
835
Functional Details
836
Register Reload Logic
837
Counter Synchronization
837
PWM Generation
839
Output Compare Capabilities
840
Force out Logic
841
Independent or Complementary Channel Operation
842
Deadtime Insertion Logic
842
Top/Bottom Correction
844
Manual Correction
846
Output Logic
848
Fault Protection
851
Fault Pin Filter
853
Automatic Fault Clearing
853
PWM Generator Loading
855
Load Enable
856
Load Frequency
856
Reload Flag
857
Chapter 38 Programmable Delay Block (PDB)
863
Pulse-Out Enable Register Implementation
866
Back-To-Back Acknowledgment Connections
868
DAC External Trigger Input Connections
868
Block Diagram
868
Modes of Operation
870
PDB Signal Descriptions
870
Memory Map and Register Definition
870
Functional Description
882
PDB Pre-Trigger and Trigger Outputs
882
PDB Trigger Input Source Selection
884
Updating the Delay Registers
885
Application Information
887
Impact of Using the Prescaler and Multiplication Factor on Timing Resolution
887
Chapter 39 Flextimer Module (FTM)
889
Instantiation Information
889
External Clock Options
889
Fixed Frequency Clock
890
FTM Interrupts
890
FTM Fault Detection Inputs
890
FTM Hardware Triggers
891
Input Capture Options for FTM Module Instances
891
FTM Output Triggers for Other Modules
891
FTM Global Time Base
892
FTM BDM and Debug Halt Mode
893
Flextimer Philosophy
893
Modes of Operation
896
Block Diagram
896
FTM Signal Descriptions
898
Functional Description
947
Counter Clock Source
948
Up-Down Counting
952
Free Running Counter
953
Counter Reset
954
When the TOF Bit Is Set
954
Input Capture Mode
955
Filter for Input Capture Mode
956
FTM Counter Reset in Input Capture Mode
957
Output Compare Mode
958
Edge-Aligned PWM (EPWM) Mode
959
Center-Aligned PWM (CPWM) Mode
961
Combine Mode
963
Asymmetrical PWM
970
Complementary Mode
970
Registers Updated from Write Buffers
971
CNTIN Register Update
972
MOD Register Update
972
Cnv Register Update
972
PWM Synchronization
973
Hardware Trigger
973
Software Trigger
974
Boundary Cycle and Loading Points
975
MOD Register Synchronization
976
CNTIN Register Synchronization
980
C(N)V and C(N+1)V Register Synchronization
980
OUTMASK Register Synchronization
980
INVCTRL Register Synchronization
983
SWOCTRL Register Synchronization
984
FTM Counter Synchronization
986
Software Output Control
990
Deadtime Insertion
992
Deadtime Insertion Corner Cases
994
Output Mask
995
Fault Control
996
Fault Inputs Polarity Control
999
Polarity Control
999
Features Priority
1000
Channel Trigger Output
1001
Initialization Trigger
1002
Capture Test Mode
1004
Dual Edge Capture Mode
1006
One-Shot Capture Mode
1007
Continuous Capture Mode
1008
Pulse Width Measurement
1008
Period Measurement
1010
Read Coherency Mechanism
1012
Quadrature Decoder Mode
1013
Quadrature Decoder Boundary Conditions
1017
BDM Mode
1018
Intermediate Load
1019
Global Time Base (GTB)
1021
Enabling the Global Time Base (GTB)
1022
Reset Overview
1023
Timer Overflow Interrupt
1025
Channel (N) Interrupt
1025
Fault Interrupt
1025
Initialization Procedure
1025
Chapter 40 Periodic Interrupt Timer (PIT)
1027
Block Diagram
1028
Signal Description
1029
Memory Map/Register Description
1029
PIT_MCR Field Descriptions
1030
Functional Description
1033
Chained Timers
1035
Example Configuration for Chained Timers
1036
Chapter 41 Quadrature Encoder/Decoder (ENC)
1039
Decoder Block Diagram
1040
System Block Diagram
1041
Glitch Filter
1042
Position Counter
1042
Revolution Counter
1043
Watchdog Timer
1044
Signal Descriptions
1044
Functional Description
1060
Chapter 42 Low-Power Timer (LPTMR)
1063
LPTMR Pulse Counter Input Options
1063
Modes of Operation
1064
LPTMR Signal Descriptions
1065
Detailed Signal Descriptions
1065
LPTMR Power and Reset
1070
LPTMR Prescaler/Glitch Filter
1070
Prescaler Enabled
1071
Prescaler Bypassed
1071
Glitch Filter Bypassed
1072
LPTMR Compare
1072
LPTMR Counter
1072
LPTMR Hardware Trigger
1073
LPTMR Interrupt
1073
Chapter 43 Flex Controller Area Network (Flexcan)
1075
Flexcan Signals
1076
Flexcan Module Features
1078
Modes of Operation
1080
Flexcan Signal Descriptions
1081
Memory Map/Register Definition
1082
Flexcan Memory Mapping
1082
Message Buffer Structure
1121
Rx FIFO Structure
1127
Transmit Process
1130
Arbitration Process
1131
Receive Process
1134
Matching Process
1137
Move Process
1141
Data Coherence
1143
CAN Protocol Related Features
1149
Remote Frames
1150
Overload Frames
1150
Time Stamp
1151
Arbitration and Matching Timing
1155
Clock Domains and Restrictions
1157
Modes of Operation Details
1158
Freeze Mode
1159
Module Disable Mode
1160
Doze Mode
1160
Bus Interface
1164
Initialization/Application Information
1165
Flexcan Initialization Sequence
1165
Chapter 44 Serial Peripheral Interface (SPI)
1169
TX FIFO Size
1170
RX FIFO Size
1170
Number of PCS Signals
1170
SPI Operation in Low Power Modes
1170
Using GPIO Interrupt to Wake from Stop Mode
1171
SPI Doze Mode
1171
SPI Interrupts
1171
Block Diagram
1172
Interface Configurations
1174
SPI Configuration
1174
Modes of Operation
1174
Master Mode
1175
Slave Mode
1175
External Stop Mode
1176
Module Signal Descriptions
1176
PCS0/SS-Peripheral Chip Select/Slave Select
1176
PCS5/PCSS-Peripheral Chip Select 5/Peripheral Chip Select Strobe
1177
SCK-Serial Clock
1177
SIN-Serial Input
1177
SOUT-Serial Output
1178
Functional Description
1201
Start and Stop of Module Transfers
1202
Serial Peripheral Interface (SPI) Configuration
1203
FIFO Disable Operation
1204
Transmit First in First out (TX FIFO) Buffering Mechanism
1204
Filling the TX FIFO
1205
Draining the TX FIFO
1205
Receive First in First out (RX FIFO) Buffering Mechanism
1205
Filling the RX FIFO
1206
Draining the RX FIFO
1206
Module Baud Rate and Clock Delay Generation
1206
Baud Rate Generator
1207
After SCK Delay
1208
Peripheral Chip Select Strobe Enable (PCSS )
1209
Transfer Formats
1210
Classic SPI Transfer Format (CPHA = 0)
1211
Classic SPI Transfer Format (CPHA = 1)
1212
Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
1213
Modified SPI Transfer Format (MTFE = 1, CPHA = 1)
1215
Continuous Selection Format
1217
Continuous Serial Communications Clock
1219
Slave Mode Operation Constraints
1221
Interrupts/Dma Requests
1221
End of Queue Interrupt Request
1222
Transmit FIFO Fill Interrupt or DMA Request
1222
Power-Saving Features
1223
Stop Mode (External Stop Mode)
1224
Initialization/Application Information
1224
How to Manage Queues
1225
Switching Master and Slave Mode
1225
Initializing Module in Master/Slave Modes
1226
Baud Rate Settings
1226
Delay Settings
1227
Calculation of FIFO Pointer Addresses
1228
Chapter 45 Inter-Integrated Circuit (I2C)
1231
Chip-Specific I2C Information
1231
Modes of Operation
1232
I 2 C Signal Descriptions
1233
I2C Address Register 1 (I2C_A1)
1234
I2C Control Register 1 (I2C_C1)
1236
I2C Status Register (I2C_S)
1237
I2C Data I/O Register (I2C_D)
1239
I2C Control Register 2 (I2C_C2)
1240
I2C Range Address Register (I2C_RA)
1242
I2C Smbus Control and Status Register (I2C_SMB)
1243
I2C Address Register 2 (I2C_A2)
1245
I2C SCL Low Timeout Register High (I2C_SLTH)
1245
Functional Description
1246
START Signal
1247
Slave Address Transmission
1247
Data Transfers
1248
STOP Signal
1248
Repeated START Signal
1249
Arbitration Procedure
1249
Clock Synchronization
1249
Clock Stretching
1250
I2C Divider and Hold Values
1250
10-Bit Address
1252
Master-Transmitter Addresses a Slave-Receiver
1252
Master-Receiver Addresses a Slave-Transmitter
1252
Address Matching
1253
System Management Bus Specification
1254
SCL Low Timeout
1254
SCL High Timeout
1255
CSMBCLK TIMEOUT MEXT and CSMBCLK TIMEOUT SEXT
1255
FAST ACK and NACK
1256
Byte Transfer Interrupt
1257
Address Detect Interrupt
1257
Stop Detect Interrupt
1258
Exit from Low-Power/Stop Modes
1258
Arbitration Lost Interrupt
1258
Timeout Interrupt in Smbus
1259
Programmable Input Glitch Filter
1259
Address Matching Wake-Up
1259
Chapter 46 Universal Asynchronous Receiver/Transmitter
1265
UART Signals
1265
UART Wakeup
1266
UART Interrupts
1266
Modes of Operation
1268
UART Signal Descriptions
1269
Transmitter Character Length
1295
Transmission Bit Order
1296
Character Transmission
1296
Transmitting Break Characters
1297
Idle Characters
1298
Hardware Flow Control
1299
Transceiver Driver Enable
1299
Receiver Character Length
1301
Receiver Bit Ordering
1302
Character Reception
1302
Data Sampling
1302
Framing Errors
1307
Receiving Break Characters
1307
Baud Rate Tolerance
1309
Slow Data Tolerance
1309
Fast Data Tolerance
1310
Receiver Wakeup
1311
Idle Input Line Wakeup (C1[WAKE] = 0)
1311
Address Mark Wakeup (C1[WAKE] = 1)
1312
Match Address Operation
1312
Baud Rate Generation
1313
Data Format
1315
Eight-Bit Configuration
1315
Nine-Bit Configuration
1316
Timing Examples
1317
Nine-Bit Format with Parity Enabled
1318
Non-Memory Mapped Tenth Bit for Parity
1318
Single-Wire Operation
1318
Loop Operation
1319
System Level Interrupt Sources
1319
RXEDGIF Description
1320
Rxd Edge Detect Sensitivity
1320
Clearing RXEDGIF Interrupt Request
1321
Exit from Low-Power Modes
1321
Initialization Sequence
1322
Overrun (OR) Flag Implications
1323
Overrun Operation
1324
Match Address Registers
1324
Modem Feature
1324
Ready-To-Receive Using RTS
1325
Transceiver Driver Enable Using RTS
1325
Legacy and Reverse Compatibility Considerations
1326
Chapter 47 General-Purpose Input/Output (GPIO)
1327
Chip-Specific GPIO Information
1327
Number of GPIO Signals
1327
GPIO Signal Descriptions
1328
General-Purpose Input
1334
General-Purpose Output
1334
Chapter 48 JTAG Controller (JTAGC)
1337
Bypass Mode
1339
TCK-Test Clock Input
1340
TDI-Test Data Input
1340
TDO-Test Data Output
1340
Register Description
1340
Instruction Register
1340
Bypass Register
1341
Device Identification Register
1341
Boundary Scan Register
1342
JTAGC Reset Configuration
1342
TAP Controller State Machine
1343
Enabling the TAP Controller
1344
JTAGC Block Instructions
1345
IDCODE Instruction
1346
SAMPLE/PRELOAD Instruction
1346
SAMPLE Instruction
1347
HIGHZ Instruction
1347
CLAMP Instruction
1347
BYPASS Instruction
1348
Boundary Scan
1348
Appendix A Release Notes
1349
AIPS Module Changes
1352
DMAMUX Module Changes
1352
PIT Module Changes
1355
LPTMR Changes
1355
UART Changes
1356
GPIO Changes
1356
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