The Debug Port; Jtag-To-Swd Change Sequence - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Table 9-1. Debug Components Description (continued)

FPB (Flash Patch and Breakpoints)

TPIU (Trace Port Inteface Unit)

MCM (Miscellaneous Control Module)

9.1.1 References

For more information on ARM debug components, see these documents:

• ARMv7-M Architecture Reference Manual

• ARM Debug Interface v5.1

• ARM CoreSight Architecture Specification

9.2 The Debug Port

1. Send more than 50 TCK cycles with TMS (SWDIO) =1

2. Send the 16-bit sequence on TMS (SWDIO) = 0111_1001_1110_0111 (MSB

transmitted first)

3. Send more than 50 TCK cycles with TMS (SWDIO) =1

See the ARM documentation for the CoreSight DAP Lite for

restrictions.

Freescale Semiconductor, Inc.

The FPB implements hardware breakpoints and patches code

and data from code space to system space.

The FPB unit contains two literal comparators for matching

against literal loads from Code space, and remapping to a

corresponding area in System space.

The FBP also contains six instruction comparators for

matching against instruction fetches from Code space, and

remapping to a corresponding area in System space.

Alternatively, the six instruction comparators can individually

configure the comparators to return a Breakpoint Instruction

(BKPT) to the processor core on a match, so providing

hardware breakpoint capability.

Asynchronous Mode (1-pin) = TRACE_SWO (available on

The MCM provides miscellaneous control functions including

control of the ETB and trace path switching.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 9 Debug