Ewm Interrupt - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description
Condition
A unique EWM service occurs when CMPL
< Counter < CMPH.
A unique EWM service occurs when
Counter < CMPL
Counter value reaches CMPH prior to a
unique EWM service
Any illegal service on EWM has no effect on EWM_out.

24.5.6 EWM Interrupt

When EWM_out is asserted, an interrupt request is generated to indicate the assertion of
the EWM reset out signal. This interrupt is enabled when CTRL[INTEN] is set. Clearing
this bit clears the interrupt request but does not affect EWM_out. The EWM_out signal
can be deasserted only by forcing a system reset.
460
Table 24-9. EWM Refresh Mechanisms
Mechanism
The software behaves as expected and the counter of the EWM is reset to zero,
and EWM_out pin remains in the deasserted state.
Note: EWM_in pin is also assumed to be in the deasserted state.
The software services the EWM and therefore resets the counter to zero and
asserts the EWM_out pin (irrespective of the EWM_in pin). The EWM_out pin is
expected to gate critical safety circuits.
The counter value reaches the CMPH value and no service of the EWM resets
the counter to zero and assert the EWM_out pin (irrespective of the EWM_in
pin). The EWM_out pin is expected to gate critical safety circuits.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.