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Functional description
19.5 Functional description
Thie low-leakage wakeup unit (LLWU) module allows internal peripherals and external
input pins as a source of wakeup from low-leakage modes.
It is operational only in VLLSx modes.
The LLWU module contains pin enables for each external pin and internal module. For
each external pin, the user can disable or select the edge type for the wakeup with the
following options:
• Falling-edge
• Rising-edge
• Either-edge
When an external pin is enabled as a wakeup source, the pin must be configured as an
input pin.
The LLWU implements optional 3-cycle glitch filters, based on the LPO clock. A
detected external pin is required to remain asserted until the enabled glitch filter times
out. Additional latency of up to 2 cycles is due to synchronization, which results in a total
of up to 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset
event when the filter function is enabled. Four wakeup detect filters are available for
selected external pins. Glitch filtering is not provided on the internal modules.
For internal module interrupts, the WUMEx bit enables the associated module interrupt
as a wakeup source.
19.5.1 VLLS modes
For any wakeup from VLLS, recovery is always via a reset flow and
RCM_SRS[WAKEUP] is set indicating the low-leakage mode was active. State retention
data is lost and I/O will be restored after PMC_REGSC[ACKISO] has been written.
A VLLS exit event due to RESET pin assertion causes an exit via a system reset. State
retention data is lost and the I/O states immediately return to their reset state. The
RCM_SRS[WAKEUP] and RCM_SRS[PIN] bits are set and the system executes a reset
flow before CPU operation begins with a reset vector fetch.
328
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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