Memory Map And Register Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

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The core clock is gated off. System clocks to other masters and bus clocks are gated off after all

stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low

leakage mode by powering down the internal logic. All system RAM contents are retained and I/O

states are held. Internal logic states are not retained.

The core clock is gated off. System clocks to other masters and bus clocks are gated off after all

stop acknowledge signals from supporting peripherals are valid.The MCU is placed in a low leakage

mode by powering down the internal logic and the system RAM3 partition. The system RAM2

partition can be optionally retained using STOPCTRL[RAM2PO]. The system RAM1 partition

contents are retained in this mode. Internal logic states are not retained.

The core clock is gated off. System clocks to other masters and bus clocks are gated off after all

stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low

leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal

logic states are not retained.

The core clock is gated off. System clocks to other masters and bus clocks are gated off after all

stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low

leakage mode by powering down the internal logic and all system RAM. I/O states are held. Internal

logic states are not retained. The 1kHz LPO clock is disabled and the power on reset (POR) circuit

can be optionally enabled using STOPCTRL[PORPO].

1. See the devices' chip configuration details for the size and location of the system RAM partitions.

16.3 Memory map and register descriptions

Information about the registers related to the system mode controller can be found here.

Different SMC registers reset on different reset types. Each register's description provides

details. For more information about the types of reset on this chip, refer to the Reset

section details.

The SMC registers can be written only in supervisor mode.

Write accesses in user mode are blocked and will result in a bus

Before executing the WFI instruction, the last register written to

must be read back. This ensures that all register writes

associated with setting up the low power mode being entered

have completed before the MCU enters the low power mode.

Failure to do this may result in the low power mode not being

entered correctly.

Freescale Semiconductor, Inc.

Table 16-1. Power modes (continued)

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 16 System Mode Controller (SMC)