Power Modes Shutdown Sequencing - NXP Semiconductors freescale KV4 Series Reference Manual

7.5 Power modes shutdown sequencing

When entering stop or other low-power modes, the clocks are shut off in an orderly
sequence to safely place the chip in the targeted low-power state. All low-power entry
sequences are initiated by the core executing an WFI instruction. The ARM core's
outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes:
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP
• All other low power modes equate to: SLEEPING & SLEEPDEEP
When entering the non-wait modes, the chip performs the following sequence:
• Shuts off Core Clock and System Clock to the ARM Cortex-M4 core immediately.
• Polls stop acknowledge indications from the non-core crossbar masters (DMA),
supporting peripherals (SPI, PIT) and the Flash Controller for indications that System
Clocks, Bus Clock and/or Flash Clock need to be left enabled to complete a
previously initiated operation, effectively stalling entry to the targeted low power
mode. When all acknowledges are detected, System Clock, Bus Clock and Flash
Clock are turned off at the same time.
• MCG and Mode Controller shut off clock sources and/or the internal supplies driven
from the on-chip regulator as defined for the targeted low power mode.
In wait modes, most of the system clocks are not affected by the low power mode entry.
The Core Clock to the ARM Cortex-M4 core is shut off. Some modules support stop-in-
wait functionality and have their clocks disabled under these configurations.
The debugger modules support a transition from stop, wait, VLPS, and VLPW back to a
halted state when the debugger is enabled. This transition is initiated by setting the Debug
Request bit in MDM-AP control register. As part of this transition, system clocking is re-
established and is equivalent to normal run/VLPR mode clocking configuration.
7.6 Clock Gating
To conserve power, the clocks to most modules can be turned off using the SCGCx
registers in the SIM module. These bits are cleared after any reset, which disables the
clock to the corresponding module. Prior to initializing a module, set the corresponding
bit in the SCGCx register to enable the clock. Before turning off the clock, make sure to
disable the module. For more details, refer to the clock distribution and SIM chapters.
Freescale Semiconductor, Inc.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 7 Power Management
113