Clock Domains And Restrictions - NXP Semiconductors freescale KV4 Series Reference Manual

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The duration of an Arbitration process, in terms of CAN bits, is directly proportional to

the number of available MBs and to the CAN bit rate, and inversely proportional to the

peripheral clock frequency.

The optimal Arbitration timing is that in which the last MB is scanned right before the

first bit of the Intermission field of a CAN frame. For instance, if there are few MBs and

the peripheral/oscillator clock ratio is high and the CAN baud rate is low, then the

Arbitration can be placed closer to the frame's end, adding more delay to its start point,

and vice-versa.

If TASD is set to 0 then the Arbitration start is not delayed and more time is reserved for

Arbitration. On the other hand, if TASD is close to 24 then the CPU can configure a Tx

MB later and less time is reserved for Arbitration. If too little time is reserved for

Arbitration the FlexCAN may be not be able to find a winner MB in time to be

transmitted with the best chance to win the bus arbitration against external nodes on the

The optimal TASD value can be calculated as follows:

• MAXMB is the value in CAN_CTRL1[MAXMB] field

is the oscillator clock, in Hz

is the peripheral clock, in Hz

• RFEN is the value in CAN_CTRL1[RFEN] bit

• RFFN is the value in CAN_CTRL2[RFFN] field

• PSEG1 is the value in CAN_CTRL1[PSEG1] field

• PSEG2 is the value in CAN_CTRL1[PSEG2] field

• PROPSEG is the value in CAN_CTRL1[PROPSEG] field

• PRESDIV is the value in CAN_CTRL1[PRESDIV] field

43.5.9 Clock domains and restrictions

The FlexCAN module has two clock domains asynchronous to each other:

Freescale Semiconductor, Inc.

f CANCLK x [ MAXMB + 3 - (RFEN x 8) - (RFEN x RFFN x 2) ] x 2

x [1 + (PSEG1 + 1) + (PSEG2 + 1) + (PROPSEG + 1) ] x (PRESDIV + 1)

for more details.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 43 Flex Controller Area Network (FlexCAN)