Interface Configurations; Spi Configuration; Modes Of Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Interface configurations

• Support for Stop mode
• Support for Doze mode
44.2.3 Interface configurations

44.2.3.1 SPI configuration

The Serial Peripheral Interface (SPI) configuration allows the module to send and receive
serial data. This configuration allows the module to operate as a basic SPI block with
internal FIFOs supporting external queue operation. Transmitted data and received data
reside in separate FIFOs. The host CPU or a DMA controller read the received data from
the Receive FIFO and write transmit data to the Transmit FIFO.
For queued operations, the SPI queues can reside in system RAM, external to the module.
Data transfers between the queues and the module FIFOs are accomplished by a DMA
controller or host CPU. The following figure shows a system example with DMA, SPI,
and external queues in system RAM.
System RAM
RX Queue
TX Queue

44.2.4 Modes of Operation

The module supports the following modes of operation that can be divided into two
categories:
• Module-specific modes:
1174
Addr/Ctrl
Rx Data
Tx Data
Tx Data
SPI
TX FIFO
Shift Register
Figure 44-2. SPI with queues and DMA
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Done
DMA Controller
or host CPU
Addr/Ctrl
Rx Data
Req
RX FIFO
Freescale Semiconductor, Inc.