Stop Detect Interrupt; Exit From Low-Power/Stop Modes; Arbitration Lost Interrupt - NXP Semiconductors freescale KV4 Series Reference Manual

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Functional description

45.5.6.3 Stop Detect Interrupt

When the stop status is detected on the I

interrupted, provided the IICIE and SSIE bits are both set to 1.

The slave receive input detect circuit and address matching feature are still active on low

power modes (wait and stop). An asynchronous input matching slave address or general

call address brings the CPU out of low power/stop mode if the interrupt is not masked.

Therefore, TCF and IAAS both can trigger this interrupt.

The I2C is a true multimaster bus that allows more than one master to be connected on it.

If two or more masters try to control the bus at the same time, the relative priority of the

contending masters is determined by a data arbitration procedure. The I2C module asserts

the arbitration-lost interrupt when it loses the data arbitration process and the ARBL bit

in the Status Register is set.

Arbitration is lost in the following circumstances:

1. SDA is sampled as low when the master drives high during an address or data

transmit cycle.

2. SDA is sampled as low when the master drives high during the acknowledge bit of a

data receive cycle.

3. A START cycle is attempted when the bus is busy.

4. A repeated START cycle is requested in slave mode.

5. A STOP condition is detected when the master did not request it.

The ARBL bit must be cleared (by software) by writing 1 to it.

C bus, the STOPF bit is set to 1. The CPU is

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.