Memory Map And Register Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA)

At reset, each output XBAR_OUT[*] contains the reset value of the signal driving

26.3.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs

This is a one-dimensional array of the mux outputs. The value on each output

XBAR_OUT[n] is determined by the setting of the corresponding memory mapped

26.3.2 XBAR_IN[0:NUM_IN-1] - MUX Inputs

This is a one-dimensional array consisting of the inputs shared by each mux. All muxes

share the same inputs in the same order.

26.3.3 DMA_REQ[n] - DMA Request Output(s)

DMA_REQ[n] is a DMA request to the DMA controller.

26.3.4 DMA_ACK[n] - DMA Acknowledge Input(s)

DMA_ACK[n] is a DMA acknowledge input from the DMA controller.

26.3.5 INT_REQ[n] - Interrupt Request Output(s)

INT_REQ[n] is an interrupt request output to the interrupt controller.

Memory Map and Register Descriptions

The XBAR module has select registers and control registers.

In the XBAR select registers, the SELn fields select which of the shared inputs

(XBAR_IN[*]) is muxed to each mux output (XBAR_OUT[*]). There is one SELn field

per mux and therefore one per XBAR_OUT output. Crossbar output XBAR_OUT[n]

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.