Can Protocol Related Features - NXP Semiconductors freescale KV4 Series Reference Manual

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updates both the FIFO output with the next message (if FIFO is not empty) and the

CAN_RXFIR register with the attributes of the new message. If there are more messages

stored in the FIFO, the CAN_IFLAG1[BUF5I] will be re-asserted and another DMA

request is issued. Otherwise, the flag remains negated.

CAN_RXFIR register contents cannot be read after DMA

completes the FIFO read. The IDHIT information is also

available in the C/S word at address 0x080 (see

The CAN_IFLAG1[BUF6I] and CAN_IFLAG1[BUF7I] are not used when the DMA

feature is enabled.

When FlexCAN is working with DMA, the CPU does not receive any Rx FIFO

interruption and must not clear the related IFLAGs. In addition, the related IMASKs are

not used to mask the generation of DMA requests.

43.5.7.2 Clear FIFO Operation

When CAN_MCR[RFEN] is asserted, the clear FIFO operation is a feature used to empty

FIFO contents. With CAN_MCR[RFEN] asserted the Clear FIFO occurs when the CPU

writes 1 in CAN_IFLAG1[BUF0I]. This operation can only be performed in Freeze

Mode and is blocked by hardware in other modes. This operation does not clear the FIFO

IFLAGs, consequently the CPU must service all FIFO IFLAGs before execute the clear

When Rx FIFO is working with DMA, the clear FIFO operation clears the

CAN_IFLAG1[BUF5I] and the DMA request is canceled.

Clear FIFO operation does not clear IFLAGs, except when

CAN_MCR[DMA] is asserted, in this case only the

CAN_IFLAG1[BUF5I] is cleared.

43.5.8 CAN protocol related features

This section describes the CAN protocol related features.

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 43 Flex Controller Area Network (FlexCAN)