Slave Mode Operation Constraints; Interrupts/Dma Requests - NXP Semiconductors freescale KV4 Series Reference Manual

SCK (CPOL = 0)
SCK (CPOL = 1)
Master SOUT
Master SIN
PCS
Figure 44-40. Continuous SCK timing diagram (CONT=1)

44.5.6 Slave Mode Operation Constraints

Slave mode logic shift register is buffered. This allows data streaming operation, when
the module is permanently selected and data is shifted in with a constant rate.
The transmit data is transferred at second SCK clock edge of the each frame to the shift
register if the SS signal is asserted and any time when transmit data is ready and SS
signal is negated.
Received data is transferred to the receive buffer at last SCK edge of each frame, defined
by frame size programmed to the CTAR0/1 register. Then the data from the buffer is
transferred to the RXFIFO or DDR register.
If the SS negates before that last SCK edge, the data from shift register is lost.

44.5.7 Interrupts/DMA requests

The module has several conditions that can generate only interrupt requests and two
conditions that can generate interrupt or DMA requests. The following table lists these
conditions.
Table 44-44. Interrupt and DMA request conditions
Condition
End of Queue (EOQ)
TX FIFO Fill
Transfer Complete
TX FIFO Underflow
Freescale Semiconductor, Inc.
transfer 1
Flag
EOQF
TFFF
TCF
TFUF
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 44 Serial Peripheral Interface (SPI)
transfer 2
Interrupt
Yes
Yes
Yes
Yes
DMA
-
Yes
-
-
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