Ftm Global Time Base - NXP Semiconductors freescale KV4 Series Reference Manual

Chip-specific FTM information
FTM0_CH2 event output to DMAMUX source 26
FTM0_CH3 event output to DMAMUX source 27
FTM0_CH4 event output to DMAMUX source 28
FTM0_CH5 event output to DMAMUX source 29
FTM0_CH6 event output to DMAMUX source 30
FTM0_CH7 event output to DMAMUX source 31
FTM1 has 2 channels of trigger capability which are ORed together to force an output
trigger. This EXTRRG1 signal is connected to PDB0 channel 1001 input, PDB1 channel
1001 input, XBARA_IN36 and XBARB_IN16.
FTM1_CH0 event output to DMAMUX source 32, UART0TXSRC and UART1TXSRC
of SIM_OPTx register.
FTM1_CH1 event output to DMAMUX source 33
FTM3 has 8 channels of trigger capability which are ORed together to force an output
trigger. This EXTTRG3 signal is connected to PDB0 channel 1011 input, PDB1 channel
1011 input, XBARA_IN18 and XBARB_IN6.
FTM3_CH0 event output to DMAMUX source 36
FTM3_CH1 event output to DMAMUX source 37
FTM3_CH2 event output to DMAMUX source 38
FTM3_CH3 event output to DMAMUX source 39
FTM3_CH4 event output to DMAMUX source 54
FTM3_CH5 event output to DMAMUX source 55
FTM3_CH6 event output to DMAMUX source 56
FTM3_CH7 event output to DMAMUX source 57

39.1.9 FTM Global Time Base

This chip provides the optional FTM global time base feature (see Global time base
(GTB)).
FTM0 provides the only source for the FTM global time base. The other FTM modules
can share the time base as shown in the following figure:
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
892 Freescale Semiconductor, Inc.