Bdm Mode - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

Figure 39-259. Motor position jittering near maximum and minimum count value

The first highlighted transition causes a jitter on the FTM counter value near the

maximum count value (MOD). The second indicated transition occurs on phase A and

causes the FTM counter transition between the maximum and minimum count values

which are defined by MOD and CNTIN registers.

The appropriate settings of the phase A and phase B input filters are important to avoid

glitches that may cause oscillation on the FTM counter value. The preceding figures

show examples of oscillations that can be caused by poor input filter setup. Thus, it is

important to guarantee a minimum pulse width to avoid these oscillations.

39.5.26 BDM mode

When the chip is in BDM mode, the BDMMODE[1:0] bits select the behavior of the

FTM counter, the CH(n)F bit, the channels output, and the writes to the MOD, CNTIN,

and C(n)V registers according to the following table.

Table 39-254. FTM behavior when the chip Is in BDM mode

CH(n)F Bit FTM Channels Output

can be set Functional mode

The channels outputs are forced

to their safe value according to

The channels outputs are frozen

when the chip enters in BDM

Table continues on the next page...

KV4x Reference Manual, Rev. 2, 02/2015

Writes to MOD, CNTIN, and C(n)V Registers

Writes to these registers bypass the registers

Writes to these registers bypass the registers

Writes to these registers bypass the registers

Freescale Semiconductor, Inc.