Baud Rate Generator - NXP Semiconductors freescale KV4 Series Reference Manual

44.5.3.1 Baud rate generator

The baud rate is the frequency of the SCK. The protocol clock is divided by a prescaler
(PBR) and scaler (BR) to produce SCK with the possibility of halving the scaler division.
The DBR, PBR, and BR fields in the CTARs select the frequency of SCK by the formula
in the BR field description. The following table shows an example of how to compute the
baud rate.
f PBR
P
100 MHz 0b00
20 MHz 0b00
The clock frequencies mentioned in the preceding table are
given as an example. Refer to the clocking chapter for the
frequency used to drive this module in the device.
44.5.3.2 PCS to SCK Delay (t
The PCS to SCK delay is the length of time from assertion of the PCS signal to the first
SCK edge. See Figure 44-29
and CSSCK fields in the CTARx registers select the PCS to SCK delay by the formula in
the CSSCK field description. The following table shows an example of how to compute
the PCS to SCK delay.
Table 44-39. PCS to SCK delay computation example
f PCSSCK
SYS
100 MHz 0b01
The clock frequency mentioned in the preceding table is given
as an example. Refer to the clocking chapter for the frequency
used to drive this module in the device.
Freescale Semiconductor, Inc.
Table 44-38. Baud rate computation example
Prescaler BR
2 0b0000
2 0b0000
NOTE
)
CSC
for an illustration of the PCS to SCK delay. The PCSSCK
Prescaler
3
NOTE
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 44 Serial Peripheral Interface (SPI)
Scaler DBR
2 0
2 1
CSSCK Scaler
0b0100 32
Baud rate
25 Mb/s
10 Mb/s
PCS to SCK Delay
0.96 μs
1207