Clearing Rxedgif Interrupt Request; Exit From Low-Power Modes - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

46.7.1.2 Clearing RXEDGIF interrupt request

Writing a logic 1 to S2[RXEDGIF] immediately clears the RXEDGIF interrupt request

even if the RxD input remains asserted. S2[RXEDGIF] remains set if another active edge

is detected on RxD while attempting to clear S2[RXEDGIF] by writing a 1 to it.

The receive input active edge detect circuit is still active on low power modes (Wait and

Stop). An active edge on the receive input brings the CPU out of low power mode if the

interrupt is not masked (S2[RXEDGIF] = 1).

46.8 DMA operation

In the transmitter, S1[TDRE] can be configured to assert a DMA transfer request. In the

receiver, S1[RDRF],and S2[LBKDIF] can be configured to assert a DMA transfer

request. The following table shows the configuration field settings required to configure

each flag for DMA operation.

When a flag is configured for a DMA request, its associated DMA request is asserted

when the flag is set. When S1[RDRF] is configured as a DMA request, the clearing

mechanism of reading S1, followed by reading D, does not clear the associated flag. The

DMA request remains asserted until an indication is received that the DMA transactions

are done. When this indication is received, the flag bit and the associated DMA request is

cleared. If the DMA operation failed to remove the situation that caused the DMA

request, another request is issued.

46.9 Application information

This section describes the UART application information.

Freescale Semiconductor, Inc.

Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI

Table 46-80. DMA configuration

Request enable bit

KV4x Reference Manual, Rev. 2, 02/2015

DMA select bit

LBKDDMAS = 1