Software Trigger - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

In this case, if two or more hardware triggers are enabled (for example, TRIG0 and

TRIG1 = 1) and only trigger 1 event occurs, then only TRIG1 bit is cleared. If a trigger n

event occurs together with a write setting TRIGn bit, then the synchronization is initiated,

but TRIGn bit remains set due to the write operation.

system clock

write 1 to TRIG0 bit

trigger_0 input

synchronized trigger_0

by system clock

trigger 0 event

All hardware trigger inputs have the same behavior.

Figure 39-207. Hardware trigger event with HWTRIGMODE = 0

If HWTRIGMODE = 1, then the TRIGn bit is only cleared when 0 is written to it.

The HWTRIGMODE bit must be 1 only with enhanced PWM

synchronization (SYNCMODE = 1).

39.5.11.2 Software trigger

A software trigger event occurs when 1 is written to the SYNC[SWSYNC] bit. The

SWSYNC bit is cleared when 0 is written to it or when the PWM synchronization,

initiated by the software event, is completed.

If another software trigger event occurs (by writing another 1 to the SWSYNC bit) at the

same time the PWM synchronization initiated by the previous software trigger event is

ending, a new PWM synchronization is started and the SWSYNC bit remains equal to 1.

If SYNCMODE = 0 then the SWSYNC bit is also cleared by FTM according to

PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and

REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the

software trigger event occurred; see

figure. If (PWMSYNC = 0) and (REINIT = 1) then SWSYNC bit is cleared when the

software trigger event occurs.

Boundary cycle and loading points

KV4x Reference Manual, Rev. 2, 02/2015

and the following

Freescale Semiconductor, Inc.