Fast Data Tolerance - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
RECEIVER
RT CLOCK
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles
(9 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the
cycles at the point when the count of the transmitting device is 147 RT cycles (9 bit times
× 16 RT cycles + 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 8-bit data character with no errors is:
((154 − 147) ÷ 154) × 100 = 4.54%
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles
(10 bit times × 16 RT cycles + 10 RT cycles).
With the misaligned character shown in the
cycles at the point when the count of the transmitting device is 163 RT cycles (10 bit
times × 16 RT cycles + 3 RT cycles).
The maximum percent difference between the receiver count and the transmitter count of
a slow 9-bit character with no errors is:
((170 − 163) ÷ 170) × 100 = 4.12%

46.5.2.8.2 Fast data tolerance

The following figure shows how much a fast received frame can be misaligned. The fast
stop bit ends at RT10 instead of RT16 but is still sampled at RT8, RT9, and RT10.
RECEIVER
RT CLOCK
1310
MSB
SAMPLES
Figure 46-75. Slow data
Figure
Figure
STOP
SAMPLES
Figure 46-76. Fast data
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
STOP
DATA
46-75, the receiver counts 154 RT
46-75, the receiver counts 170 RT
IDLE OR NEXT FRAME
DATA
Freescale Semiconductor, Inc.