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Signal Descriptions
IP_bus
Note: Control field support can be restricted to a subset of outputs. CTRLn represents the memory mapped
control fields in the XBAR_CTRL registers for each corresponding XBAR_OUT output. Control fields provide
edge status, edge selection, and interrupt/DMA generation controls.
26.3 Signal Descriptions
The following table summarizes the module's external signals.
Name
XBAR_OUT
[0:NUMOUT-1]
XBAR_IN [0:NUMIN-1]
DMA_REQ
INT_REQ
DMA_ACK
488
XBAR_IN 0
XBAR_IN 1
XBAR_IN N-1
SEL 0
SEL 1
SEL M-1
Figure 26-1. XBAR Block Diagram
Table 26-3. Control Signal Properties
I/O Type
Function
O
Mux Outputs with
configurable width
I
Mux Inputs with
configurable width
O
DMA request
O
Interrupt request
I
DMA acknowledge
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
DMA_ACK 0
DMA 0
CTRL 0
M
U
X
DMA_ACK 1
DMA 1
CTRL 1
M
U
X
DMA_ACK M-1
DMA
CTRL M-1
M
U
X
Reset State
*
*
0
0
0
DMA_REQ 0
INT_REQ 0
XBAR_OUT 0
DMA_REQ 1
INT_REQ 1
XBAR_OUT 1
DMA_REQ M-1
m-1
INT_REQ M-1
XBAR_OUT M-1
Notes
Freescale Semiconductor, Inc.
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