Chapter 48 Jtag Controller (Jtagc) - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 48
JTAG Controller (JTAGC)
48.1 Introduction
The JTAGC block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a
boundary scan technique, as defined in the IEEE 1149.1-2001 standard. All data input to
and output from the JTAGC block is communicated in serial format.
48.1.1 Block diagram
The following is a simplified block diagram of the JTAG Controller (JTAGC) block.
Refer to the chip-specific configuration information as well as
more information about the JTAGC registers.
Power-on reset
TMS
TCK
TDI
Freescale Semiconductor, Inc.
Test Access Port (TAP)
1-bit Bypass Register
32-bit Device Identification Register
Boundary Scan Register
TAP Instruction Decoder
TAP Instruction Register
Figure 48-1. JTAG (IEEE 1149.1) block diagram
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Register description
Controller
for
TDO
1337