Filter For Input Capture Mode - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
synchronizer
channel (n) input
DQ
system clock
CLK
If the channel input does not have a filter enabled, then the input signal is always delayed
3 rising edges of the system clock, that is, two rising edges to the synchronizer plus one
more rising edge to the edge detector. In other words, the CHnF bit is set on the third
rising edge of the system clock after a valid edge occurs on the channel input.

39.5.4.1 Filter for Input Capture mode

The filter function is only available on channels 0, 1, 2, and 3.
First, the input signal is synchronized by the system clock. Following synchronization,
the input signal enters the filter block. See the following figure.
channel (n) input after
the synchronizer
system clock
When there is a state change in the input signal, the counter is reset and starts counting
up. As long as the new state is stable on the input, the counter continues to increment.
When the counter is equal to CHnFVAL[3:0], the state change of the input signal is
validated. It is then transmitted as a pulse edge to the edge detector.
956
DQ
Filter*
CLK
* Filtering function is only available in the inputs of channel 0, 1, 2, and 3
Figure 39-176. Input Capture mode
Logic to control
the filter counter
filter counter
divided by 4
Figure 39-177. Channel input filter
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
was rising
edge selected?
is filter
enabled?
0 0
rising edge
1
0
edge
detector
1
1
falling edge
0 0
was falling
edge selected?
CHnFVAL[3:0]
Logic to define
the filter output
channel (n) interrupt
CHnIE
CHnF
CnV
FTM counter
filter output
Q
S
C
CLK
Freescale Semiconductor, Inc.