Boundary Cycle And Loading Points - NXP Semiconductors freescale KV4 Series Reference Manual

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If SYNCMODE = 1 then the SWSYNC bit is also cleared by FTM according to the

SWRSTCNT bit. If SWRSTCNT = 0 then SWSYNC bit is cleared at the next selected

loading point after that the software trigger event occurred; see the following figure. If

SWRSTCNT = 1 then SWSYNC bit is cleared when the software trigger event occurs.

system clock

write 1 to SWSYNC bit

software trigger event

PWM synchronization

39.5.11.3 Boundary cycle and loading points

The boundary cycle definition is important for the loading points for the registers MOD,

CNTIN, and C(n)V.

mode, the boundary cycle is defined as when the counter wraps to its

initial value (CNTIN). If in

as when the counter turns from down to up counting and when from up to down counting.

The following figure shows the boundary cycles and the loading points for the registers.

In the Up Counting mode, the loading points are enabled if one of CNTMIN or CTMAX

bits are 1. In the Up-Down Counting mode, the loading points are selected by CNTMIN

and CNTMAX bits, as indicated in the figure. These loading points are safe places for

For both counting modes, if neither CNTMIN nor CNTMAX are 1, then the boundary

cycles are not used as loading points for registers updates. See the register

synchronization descriptions in the following sections for details.

Freescale Semiconductor, Inc.

Figure 39-208. Software trigger event

Up-down counting

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 39 FlexTimer Module (FTM)

selected loading point

mode, then the boundary cycle is defined