Uart Signal Descriptions - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

46.2.2.2 Wait mode

UART operation in the Wait mode depends on the state of the C1[UARTSWAI] field.

• If C1[UARTSWAI] is cleared, and the CPU is in Wait mode, the UART operates

• If C1[UARTSWAI] is set, and the CPU is in Wait mode, the UART clock generation

ceases and the UART module enters a power conservation state.

Setting C1[UARTSWAI] does not affect the state of the C2[RE] or C2[TE].

If C1[UARTSWAI] is set, any ongoing transmission or reception stops at the Wait mode

entry. The transmission or reception resumes when either an internal or external interrupt

brings the CPU out of Wait mode. Bringing the CPU out of Wait mode by reset aborts

any ongoing transmission or reception and resets the UART.

46.2.2.3 Stop mode

The UART is inactive during Stop mode for reduced power consumption. The STOP

instruction does not affect the UART register states, but the UART module clock is

disabled. The UART operation resumes after an external interrupt brings the CPU out of

Stop mode. Bringing the CPU out of Stop mode by reset aborts any ongoing transmission

or reception and resets the UART.

46.3 UART signal descriptions

The UART signals are shown in the following table.

Clear to send

Request to send

Receive data

Transmit data

46.3.1 Detailed signal descriptions

The detailed signal descriptions of the UART are shown in the following table.

Freescale Semiconductor, Inc.

Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI

Table 46-1. UART signal descriptions

KV4x Reference Manual, Rev. 2, 02/2015