Modes Of Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

37.2.1 Features

• 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs

• Fractional PWM clock generation for enhanced resolution of the PWM period and

• Dithering to simulate enhanced resolution when fine edge placement is not available

• PWM outputs that can operate as complementary pairs or independent channels

• Ability to accept signed numbers for PWM generation

• Independent control of both edges of each PWM output

• Support for synchronization to external hardware or other PWM

• Double buffered PWM registers

• Integral reload rates from 1 to 16

• Half cycle reload capability

• Multiple output trigger events can be generated per PWM cycle via hardware

• Support for double switching PWM outputs

• Fault inputs can be assigned to control multiple PWM outputs

• Programmable filters for fault inputs

• Independently programmable PWM output polarity

• Independent top and bottom deadtime insertion

• Each complementary pair can operate with its own PWM frequency and deadtime

• Individual software control for each PWM output

• All outputs can be programmed to change simultaneously via a FORCE_OUT event

• PWM_X pin can optionally output a third PWM signal from each submodule

• Channels not used for PWM generation can be used for buffered output compare

• Channels not used for PWM generation can be used for input capture functions

• Enhanced dual edge capture functionality

• The option to supply the source for each complementary PWM signal pair from any

of the following:

• Crossbar module outputs

• External ADC input, taking into account values set in ADC high and low limit

37.2.2 Modes of Operation

Be careful when using this module in stop, wait and debug operating modes.

Freescale Semiconductor, Inc.

Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM)

KV4x Reference Manual, Rev. 2, 02/2015