Jtag Reset; Ntrst Reset; Resetting The Debug Subsystem - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

10.2.3.1 JTAG reset

The JTAG module generate a system reset when certain IR codes are selected. This

functional reset is asserted when EXTEST, HIGHZ and CLAMP instructions are active.

The reset source from the JTAG module is released when any other IR code is selected.

A JTAG reset causes the SRSH[JTAG] bit to set.

The nTRST pin causes a reset of the JTAG logic when asserted. Asserting the nTRST pin

allows the debugger to gain control of the TAP controller state machine (after exiting

LLS or VLLSx) without resetting the state of the debug modules.

The nTRST pin does not cause a system reset.

Use the CDBGRSTREQ bit within the SWJ-DP CTRL/STAT register to reset the debug

modules. However, as explained below, using the CDBGRSTREQ bit does not reset all

debug-related registers.

CDBGRSTREQ resets the debug-related registers within the following modules:

• ATB replicators

• ATB upsizers

• ATB funnels

• MDM-AP (MDM control and status registers)

CDBGRSTREQ does not reset the debug-related registers within the following modules:

• CM7 core (core debug registers: DHCSR, DCRSR, DCRDR, DEMCR)

• Crossbar bus switch

1. CDBGRSTREQ does not affect AHB resources so that debug resources on the private peripheral bus are available

during System Reset.

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.