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• Windowed refresh option
• Provides robust check that program flow is faster than expected.
• Programmable window.
• Refresh outside window leads to reset.
• Robust refresh mechanism
• Write values of 0xA602 and 0xB480 to WDOG Refresh Register within 20 bus
clock cycles.
• Count of WDOG resets as they occur.
• Configurable interrupt on time-out to provide debug breadcrumbs. This is followed
by a reset after 256 bus clock cycles.
25.4 Functional overview
Freescale Semiconductor, Inc.
Reading the watchdog timer counter while running the
watchdog on the bus clock might not give the accurate
counter value.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 25 Watchdog Timer (WDOG)
NOTE
463
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